Semiconductor Engineering

Enhancing Silicon Reliability With In-System Test And SLM Data

A convergence of DFT techniques and the proliferation of in-silicon monitors can flag potential failures before they occur.
Semiconductor Engineering

AI Accelerators Usher In New Era For IC Test

The number and variety of test interfaces, coupled with increased packaging complexity, are adding a slew of new challenges.
Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

Take scan test out of the critical path

Integrated circuit complexity and integration continuously advances, posing challenges to the development process. Market profitability, however, demands that products be designed and produced as fast ...
EDN

DFT software tackles test costs

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's ...